(a) Field of the Invention
The present invention relates to a wiring board in which a capacitor is mounted. More particularly, the present invention relates to a novel structure of a wiring board in which a decoupling capacitor is mounted, for mounting a semiconductor element (chip), an electronic component, or the like, required to perform a high-speed switching operation, and to a method of manufacturing the same.
In this specification, for convenience, a wiring board is also referred to as a “semiconductor package” in the sense that it plays a role as a package on which a semiconductor element or the like is mounted. Further, a wiring board (semiconductor package) in a state of having a semiconductor element or the like mounted thereon is referred to as a “semiconductor device.”
(b) Description of the Related Art
In recent years, for printed wiring boards, weight reduction is required, and finer and denser wiring is required in order to mount a ball grid array (BGA), a pin grid array (PGA), a chip size package (CSP), or the like, which have been miniaturized and come to have a large number of pins. However, since conventional printed wiring boards have needed large areas for the formation of via holes, flexibility in design has been limited, and finer wiring has been difficult to realize. In view of this background, the commercialization of printed wiring boards (build-up multilayer wiring boards) by build-up processes has been recently advanced. As the build-up multilayer wiring boards, various types can be fabricated depending on a combination of material for an interlayer insulating layer and a via hole formation process. In a basic process thereof, conductor layers are stacked by sequentially repeating the formation of an insulating layer, the formation of via holes for interlayer connection in the insulating layer, and the formation of a conductor layer (patterned interconnections, pads, and the like) including the insides of the via holes. In a multilayer wiring board obtained by such a build-up process, even a semiconductor element (chip) having an advanced integration degree and the like can be mounted.
However, on the other hand, since wiring patterns are close to each other in such a multilayer wiring board (semiconductor package), problems can occur, such as an occurrence of crosstalk noise between the wiring patterns, a fluctuation in the potential of a power supply line or a ground line, and the like. In particular, in a semiconductor package in which a semiconductor element, an electronic component, or the like, required to perform a high-speed switching operation, is mounted, the tendency of crosstalk noise to occur increases as the frequency increases. Further, switching noise occurs due to a switching element turning on and off at high speed, and this makes the potentials of a power supply line and the like ready to fluctuate. This leads to a deterioration in the operational reliability of the mounted semiconductor element or the like, and therefore is not preferable.
In view of this background, in order to stabilize the power supply voltage and reduce switching noises and the like, “decoupling” a power supply line and the like has been heretofore performed by attaching a capacitive element such as a chip capacitor to a semiconductor package in which a semiconductor element is mounted. As a typical technique, there is a method in which a chip capacitor is surface-mounted by soldering or the like on the same surface as or the opposite surface to the surface on which the semiconductor element or the like is mounted, of the semiconductor package.
However, in this case, the total thickness of the package increases by an amount corresponding to the provision of the capacitor on the surface of the semiconductor package. Further, the routing length of interconnections connecting the capacitor and the semiconductor element increases, and this may cause an increase in inductance. Since effective “decoupling” cannot be performed when inductance is large, it is desirable that inductance be as small as possible. To this end, it is desirable that the capacitor be placed as close to the semiconductor element as possible. Further, placing the capacitor close to the semiconductor element as described above has been regarded as a technical common sense.
Technologies relating to the above-described conventional technology include, for example, as described in Japanese unexamined Patent Publication (JPP) 11-68319, a technology in which a decoupling capacitor is incorporated into a resin multilayer circuit board obtained by a build-up process and in which a dielectric layer sandwiched between two layers of conductor patterns constituting the capacitor is formed of material (resin) having a relative dielectric constant of a predetermined value or more.
In the conventional technologies as described above, in order to make the inductance of a decoupling capacitor as small as possible, the routing length between the capacitor and a semiconductor element has been made as short as possible by placing the capacitor close to the semiconductor element. In this case, consideration has not been given to the magnetic coupling between a current flowing through the capacitor and a plane-shaped wiring pattern in the vicinity thereof, particularly, a power supply plane or a ground plane.
Accordingly, under the condition that the routing length between the capacitor and the semiconductor element is merely short when the capacitor and the semiconductor element are connected, there may be cases where the equivalent series inductance (ESL) of the capacitor cannot be necessarily reduced. For example, in the case where there is a plane-shaped wiring pattern connected to a long plate-shaped chip capacitor in the vicinity of the capacitor, where the wiring pattern is parallel to the longitudinal direction of the capacitor, and where the direction of a current flowing through the capacitor and that of a current flowing through the wiring pattern are the same, the direction of a magnetic field generated by the current flowing through the capacitor and that of a magnetic field generated by the current flowing through the wiring pattern become the same. Accordingly, as for the ESL of the capacitor, the apparent inductance becomes large under the influence of the magnetic field originating from the wiring pattern.
Namely, there has been a problem in that the ESL of the capacitor cannot be necessarily sufficiently reduced depending on the relationship between the placement of the capacitor and that of a wiring pattern in the vicinity thereof and the relationship between the directions of currents flowing therethrough.